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DS_6612_001
78M6612 Data Sheet
2.2
2.2.1
Fault and Reset Behavior
Reset Mode
When the RESET pin is pulled high, all digital activity stops. The oscillator and RTC module continue to
run. Additionally, all I/O RAM bits are set to their default states. As long as V1, the input voltage at the
power fault block, is greater than VBIAS, the internal 2.5 V regulator continues to provide power to the
digital section.
Once initiated, the reset mode persists until the reset timer times out. This occurs in 4096 cycles of the
real time clock after RESET goes low, at which time the MPU begins executing its preboot and boot
sequences from address 00.
2.2.2
Power Fault Circuit
The 78M6612 includes a comparator to monitor system power fault conditions. When the output of the
comparator falls (V1<VBIAS), the PLL status bits in the I/O RAM are zeroed and the IC power downs.
Once system power returns, the MPU remains in reset and does not start until 2048 to 4096 CK32 clock
cycles later. Program execution starts at address 0x00. MPU RAM will be re-initialized.
2.3
Data Flow
IA, VA, IB, and VB, performing calculations to measure active power (Wh), reactive power (VARh), A h,
and V h for four-quadrant measurement. These measurements are then accessed by the MPU,
The data flow between the Compute Engine (CE) and the MPU is shown in Figure 6 . In a typical
application, the 32-bit CE sequentially processes the samples from the current and voltage inputs on pins
2
2
processed further and output using the peripheral devices available to the MPU.
Pulses
IRQ
Samples
CE
Pr -
Processo
r
Data
MP
U Pos -
t
Processo
r
Processed
Metering
Data
I/O RAM (Configuration RAM)
Figure 6: MPU/CE Data Flow
Rev 2
19
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